Exercise 7 -cs621

Exercise 7

From text book chapter 4

Exercise 4.1

Different instructions utilize different hardware blocks in the basic single-cycle implementation The next three problems in this exercise refer to the following instruction

	Instruction	Interpretation
a.	Add Rd, Rs, Rt	Reg[Rd]=Reg[Rs]+Reg[Rt]
b.	Lw Rt, Offs(Rs)	Reg[Rt]=Mem[Reg[Rs]+Offs]

4.1.1 What are the values of control signals generated by the control in Figure 4.2 for this instruction?

Ans

	RegWrite	MemRead	ALUMux	MemWrite	ALUOp	RegMux	Branch
a.	1	0	0(Reg)	0	Add	1(ALU)	0
b.	1	1	1(Imm)	0	Add	1(Mem)	0

4.1.2 Which resources (blocks) perform a useful function for this instruction?

Ans

a.

ทุกอย่าง ยกเว้น Data Memory และ branch Add unit

b.

ทุกอย่าง ยกเว้น branch Add unit และ second read port of the Register

4.1.3 Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?

Ans

	Output ที่ไม่ได้ใช้งาน	ไม่มี Output
a.	Branch Add	Data Memory
b.	Branch Add,second read port of the Register	None

　

Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. For the remaining three problems in this exercise, assume the following resource latencies:

	I-Mem	Add	Mux	ALU	Regs	D-Mem	Control
a.	400ps	100ps	30ps	120ps	200ps	350ps	100ps
b.	500ps	150ps	100ps	180ps	220ps	1000ps	65ps

4.1.4 What is the critical path for a MIPS AND instruction?

Ans

a. Control

เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux

b. Control

เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux

4.1.5 What is the critical path for a MIPS load (LD) instruction?

Ans

a. Control

เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, D-Mem, Mux

b. Control

เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux

4.1.6 What is the critical path for a MIPS BEQ instruction?

Ans

a. path

แรก ยาวที่สุด(through Regs)

b. path

แรก ยาวที่สุด(through Regs)

　

Exercise 4.4

When implementing a logic expression in digital logic, one must use the available logic gates to implement an operator for which a gate is not available. Problems in this exercise refer to the following logic expressions:

	Control signal 1	Control signal 2
a.	(((A OR B) OR C) OR (A AND C)) OR (A AND B)	(A OR B) OR C
b.	(((A OR B) XOR B) OR (A OR C)) OR (A AND B)	A AND B

4.4.1 Implement the logic for the Control signal 1. Your circuit should directly implement the given expression (do not reorganize the expression to “optimize” it), using NOT gates and 2-input AND, OR, and XOR gates.

Ans

a.
                              

b.

　

4.4.2 Assuming that all gates have equal latencies, what is the length (in gates) of the critical path in your circuit from Exercise 4.4.1 ?

Ans

a. Latency in gates = 4

b. Latency in gates = 4

　

　

Exercise 4.9

In this exercise we examine the operation of the single-cycle datapath for a particular instruction. Problems in this exercise refer to the following MIPS instruction:

	Instruction
a.	lw $1,40($6)
b.	Label: bne $1,$2,Label

4.9.1 What is the value of the instruction word?

Ans

	Binary	Hexadecimal
a.	100011 00110 00001 0000000000101000	8CC10028
b.	000101 00001 00010 1111111111111111	1422FFFF

　

a. 100011 00110 00001 0000000000101000 8CC10028

b. 000101 00001 00010 1111111111111111 1422FFFF

4.9.2 What is the register number supplied to the register file’s “Read register 1” input? Is this register actually read? How about “Read register 2”?

Ans

	Read register 1	Actually read?	Read register 2	Actually read?
a.	6 (00110 b)	Yes	1 (00001 b)	Yes แต่ไม่ใช่
b.	1 (00001 b)	Yes	2 (00010 b)	Yes

4.9.3 What is the register number supplied to the register file’s “Write register” input? Is this register actually written?

　

　

　

Ans

	Read register 1	Register actually written
a.	1 (00001 b)	Yes
b.	ไม่ทราบ เนื่องจาก ไม่ทราบ Register ปลายทาง	No

　

Exercise 4.11

In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:

	Instruction word
a.	10001100010000110000000000010000
b.	00010000001000110000000000001100

4.11.1 What are the outputs of the sign-extend and the jump “Shiftleft2” unit (in the upper left of Figure 4.24) for this instruction word?

Ans

	sign-extend	jump “Shiftleft2”
a.	00000000000000000000000000010000	0001000011000000000001000000
b.	00000000000000000000000000001100	0000100011000000000000110000

4.11.2 What are the values of ALU control unit’s inputs for this instruction?

Ans

	ALU control unit	instruction
a.	00	010000
b.	01	001100

4.11.3 What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.

Ans

	new PC address	path through
a.	PC + 4	PC > Add (PC+4) > branch Mux > jump Mux > PC
b.	ถ้า $1 และ $3 ไม่เท่ากัน ให้ PC+4	PC > Add (PC+4) > branch Mux หรือ PC > Add (PC+4) > Add (adds offset) > branch Mux

The remaining problems in this exercise assume that data memory is all-zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched:

	$0	$1	$2	$3	$4	$5	$6	$8	$12	$31
a.	0	1	2	3	-4	5	6	8	1	-32
b.	0	-16	-2	-3	4	-10	-6	-1	8	-4

4.11.4 For each Mux, show the values of its data output during the execution of this instruction and these register values.

Ans

	WrReg Mux	ALU Mux	Mem/ALU Mux	Branch Mux	Jump Mux
a.	3	16	0	PC+4	PC+4
b.	3 หรือ 0	-3	x	PC+4	PC+4

4.11.5 For the ALU and the two add units, what are their data input values?

Ans

	ALU	Add(PC+4)	Add(Branch)
a.	2 และ 16	PC และ 4	PC+4 และ 16*4
b.	-16 และ -3	PC และ 4	PC+4 และ 12*4

4.11.6 What are the values of all inputs for the “Registers” unit?

Ans

	Read Register1	Read Register2	Write Register	Write Data	RegWrite
a.	2	3	3	0	1
b.	1	3	3 หรือ 0	X	0

　

Exercise 6 -cs621

Excercie Text Book (MIP Version)

2.7 The following problems explore number conversions from signed and unsigned binary number to decimal numbers.

a.       1010  1101  0001  0000  0000  0000  0000  0010two

b.       1111  1111  1111  1111  1011  0011  0101  0011two

2.7.1 For the patterns above, what base 10 number does it represent, assuming that it is a two's complement integer?

a. 1010  1101  0001  0000  0000  0000  0000  0010two   -  1

      = 1010 1101 0001 0000 0000 0000 0000 0001 two

complement

      = 0101 0010 1110 1111 1111 1111 1111 1110 two

(1x2³⁰)+ (1x2²⁸)+ (1x2²⁵)+ (1x2²³)+ (1x2²²)+ (1x2²¹)+ (1x2¹⁹)+…+(1x2⁴)+ (1x2³)+ (1x2²)+ (1x2¹)

= 1,391,460,350 ten   =>   =  -1,391,460,350 ten

b. 1111  1111  1111  1111  1011  0011  0101  0011two   -  1

      = 1111  1111  1111  1111  1011  0011  0101  0010two

complement

      = 0000  0000  0000  0000  0100  1100  1010  1100two

(1x2¹⁴)+ (1x2¹¹)+ (1x2¹⁰)+ (1x2⁷)+ (1x2⁵)+ (1x2³)+ (1x2²)

= 19,628 ten   =>   = -19,628 ten

 2.7.2 For the patterns above, what base 10 number does it represent, assuming that it is an unsigned integer?

a. 1010  1101  0001  0000  0000  0000  0000  0010two  

(1x-2³¹)+ (1x2²⁹)+ (1x2²⁷)+ (1x2²⁶)+ (1x2²⁴)+ (1x2²⁰)+ (1x2¹)

= 2,903,506,946ten

b. 1111  1111  1111  1111  1011  0011  0101  0011two  

(1x-2³¹)+ (1x2³⁰)+…+ (1x2¹⁵)+ (1x2¹³)+ (1x2¹²)+ (1x2⁹)+ (1x2⁸)+ (1x2⁶)+ (1x2⁴)+ (1x2¹)+ (1x2⁰)

= 4,294,947,667ten

2.7.3 For the patterns above, what hexadecimal number does it represent?

a. 1010  1101  0001  0000  0000  0000  0000  0010two  

= 1010 => a

    1101 => d

    0001 => 1

    0000 => 0

    0000 => 0

    0000 => 0

    0000 => 0

    0010 => 2

Ans         ad100002 hex

b. 1111  1111  1111  1111  1011  0011  0101  0011two  

= 1111 => f

    1111 => f

    1111 => f

    1111 => f

    1011 => b

    0011 => 3

    0101 => 5

    0011 => 3

Ans         fffb353 hex

The following problems explore number conversions from decimal to signed and unsigned binary numbers

a.       2147483647ten

b.       1000ten

2.7.4 For the base ten numbers above, convert to two’s complement binary

a. 2147483647ten

     Ans    1110  0000  1110  0100  1010  1111  1111  1111 two

b. 1000ten

     Ans    0000  0000  0000  0000  0000  0011  1110  1000 two

2.7.5 For the base ten numbers above, convert to two’s complement hexadecimal

a. 2147483647ten

     = 1110  0000  1110  0100  1010  1111  1111  1111 two

     = 1110 => e

         0000 => 0

         1110 => e

         0100 => 4

         1010 => a

         1111 => f

         1111 => f

         1111 => f

      = e0e4afff hex

b. 1000ten

     = 0000  0000  0000  0000  0000  0011  1110  1000 two

     = 0000 => 0

         0000 => 0

         0000 => 0

         0000 => 0

         0000 => 0

         0011 => 3

         1110 => e

         1000 => 8

     = 000003e8 hex

2.7.6 For the base ten numbers above, convert the negated values from the table to two’s complement hexadecimal

a. 2147483647ten

     = 1110  0000  1110  0100  1010  1111  1111  1111 two  -  1

     = 1110  0000  1110  0100  1010  1111  1111  1110 two

complement

     = 0001  1111  0001  1011  0101  0000  0000  0001 two

     = 0001 => 1

         1111 => f

         0001 => 1

         1011 => b

         0101 => 5

         0000 => 0

         0000 => 0

         0001 => 1

     = 1f1b5001 hex

b. 1000ten

     = 0000  0000  0000  0000  0000  0011  1110  1000 two  -  1

     = 0000  0000  0000  0000  0000  0011  1110  0001 two

complement

     = 1111  1111  1111  1111  1111  1100  0001  1110 two

     = 1111 => f

         1111 => f

         1111 => f

         1111 => f

         1111 => f

         1100 => c

         0001 => 1

         1110 => e

     = fffffc1e hex

2.9 The table below contains various values for register $s1. You will be asked to evaluate if there would be overflow for a given operation

        a. 2147483647ten

        b. 0XD0000000sixteen

2.9.1 Assume that register $s0 = 0X70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, will there be overflow?

a. 2147483647ten

     2147483647ten  = 0111  1111  1111  1111  1111  1111  1111  1111 two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     0111  1111  1111  1111  1111  1111  1111  1111 two

                                                                                                         +

     0111  0000  0000  0000  0000  0000  0000  0000 two

    1110  1111  1111  1111  1111  1111  1111  1111 two

Ans  Overflow

b. 0XD0000000sixteen

     0XD0000000sixteen   = 1101  0000  0000  0000  0000  0000  0000  0000 two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1101  0000  0000  0000  0000  0000  0000  0000 two           

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

 1 0100  0000  0000  0000  0000  0000  0000  0000 two

Ans  Overflow

2.9.2 Assume that register $s0 = 0X80000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, will there be overflow?

a. 2147483647ten

     2147483647ten  = 0111  1111  1111  1111  1111  1111  1111  1111 two

     0x80000000 = 1000  0000  0000  0000  0000  0000  0000  0000 two

     0111  1111  1111  1111  1111  1111  1111  1111 two

                                                                                                        +

     1000  0000  0000  0000  0000  0000  0000  0000 two

     1111  1111  1111  1111  1111  1111  1111  1111 two

Ans  Overflow

b. 0XD0000000sixteen

     0XD0000000sixteen   = 1101  0000  0000  0000  0000  0000  0000  0000 two

     0x80000000 = 1000  0000  0000  0000  0000  0000  0000  0000 two

     1101  0000  0000  0000  0000  0000  0000  0000 two

                                                                                                        +

     1000  0000  0000  0000  0000  0000  0000  0000 two

     1111  1111  0000  0000  0000  0000  0000  0000 two

Ans  Overflow

2.9.3 Assume that register $s0 = 0X7FFFFFFF and $s1 has the value as given in the table. If the instruction: sub $s0, $s0, $s1 is executed, will there be overflow?

a. 2147483647ten

     2147483647ten  = 0111  1111  1111  1111  1111  1111  1111  1111 two

     0x7FFFFFFF = 0111  1111  1111  1111  1111  1111  1111  1111 two

     0111  1111  1111  1111  1111  1111  1111  1111 two

                                                                                                        -

     0111  1111  1111  1111  1111  1111  1111  1111 two

     1110  0000  0000  0000  0000  0000  0000  0000two

Ans  Overflow

b. 0XD0000000sixteen

     0XD0000000sixteen   = 1101  0000  0000  0000  0000  0000  0000  0000 two

     0x7FFFFFFF = 0111  1111  1111  1111  1111  1111  1111  1111 two

     0111  1111  1111  1111  1111  1111  1111  1111two

                                                                                                        -

     1101  0000  0000  0000  0000  0000  0000  0000two

     1010  1111  1111  1111  1111  1111  1111  1111 two

Ans  Overflow

The table below contains various values for register $s1. You will be asked to evaluate if there would be overflow for a given operation

a.       1010  1101  0001  0000  0000  0000  0000  0010two

b.       1111  1111  1111  1111  1011  0011  0101  0011two

2.9.4 Assume that register $s0 = 0X70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, will there be overflow?

a. 1010  1101  0001  0000  0000  0000  0000  0010two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1010  1101  0001  0000  0000  0000  0000  0010two           

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0001  1101  0001  0000  0000  0000  0000  0010 two

Ans  Overflow

b. 1111  1111  1111  1111  1011  0011  0101  0011two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1111  1111  1111  1111  1011  0011  0101  0011two

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0110  1111  1111  1111  1011  0011  0101  0011 two

Ans  Overflow

2.9.5 Assume that register $s0 = 0X70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, what is the result in hex?

a. 1010  1101  0001  0000  0000  0000  0000  0010two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1010  1101  0001  0000  0000  0000  0000  0010two           

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0001  1101  0001  0000  0000  0000  0000  0010 two

Ans   11d100002

b. 1111  1111  1111  1111  1011  0011  0101  0011two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1111  1111  1111  1111  1011  0011  0101  0011two

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0110  1111  1111  1111  1011  0011  0101  0011 two

Ans  16fffb353

2.9.6 Assume that register $s0 = 0X70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, what is the result in base ten?

a. 1010  1101  0001  0000  0000  0000  0000  0010two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1010  1101  0001  0000  0000  0000  0000  0010two           

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0001  1101  0001  0000  0000  0000  0000  0010 two

     0001  0001  1101  0001  0000  0000  0000  0000  0010 two

     (1x2³²)+ (1x2²⁸)+ (1x2²⁷)+ (1x2²⁶)+ (1x2²⁴) + (1x2¹)

     4294967296+268435456+134217728+67108864+16777216+2

Ans   4,781,506,562 ten  

b. 1111  1111  1111  1111  1011  0011  0101  0011two

     0x70000000 = 0111  0000  0000  0000  0000  0000  0000  0000 two

     1111  1111  1111  1111  1011  0011  0101  0011two

                                                                                                          +

     0111  0000  0000  0000  0000  0000  0000  0000 two

1  0110  1111  1111  1111  1011  0011  0101  0011 two

     0001  0110  1111  1111  1111  1011  0011  0101  0011 two

     (1x2³²)+ (1x2³⁰)+ (1x2²⁹)+ (1x2²⁷)+…+ (1x2¹⁵) + (1x2¹³) + (1x2¹²) + (1x2⁹) + (1x2⁸) + (1x2⁶) + (1x2⁴) + (1x2¹) + (1x2⁰)

Ans 6,173,995,859 ten

2.10 In the following problems, the data table contains bit that represent the opcode of an instruction. You will be asked to translate the entries into assembly code and determine what format of MIPS instruction the bits represent

a. 1010  1110  0000  1011  0000  0000  0000  0100two

b. 1000  1101  0000  1000  0000  0000  0100  0000two

2.10.1 For the binary entries above, what instruction do they represent?

a.

opcode(6)	rs(5)	rt(5)	immediate(16)
101011	10000	01011	0000000000000100
Sw	16	11	4

sw  rt, immediate(rs)

sw  $11,4($16)  หรือ  sw $t3, 4($s0)

b.

opcode(6)	rs(5)	rt(5)	immediate(16)
100011	01000	01000	0000000001000000
lw	8	8	64

lw  rt, immediate(rs)

lw  $8,64($8)  หรือ  lw $t0, 64($t0)

2.10.2 What type (I-type, R-type) instruction do the binary entries above represent?

a.       I-type

b.       I-type

2.10.3 If the binary entries above were data bits, what number would they represent in hexadecimal?

a.       1010  1110  0000  1011  0000  0000  0000  0100 แปลงเป็นฐาน 16 ได้  AE0B0004

b.       1000  1101  0000  1000  0000  0000  0100  0000 แปลงเป็นฐาน 16 ได้  8D080040

In the following problems, the data table contains MIPS instruction. You will be asked to translate the entries into the bits of the opcode and determine what is the MIPS instruction format.

a.       add $t0,  $t0,  $zero

b.       lw  $t1,  4($s3)

2.10.4  For the instruction above, show the hexadecimal representation of these instructions

a.

add $t0,  $t0,  $zero	add  rd, rs, rt  100000 (R-type)
Opcode	000000two
Function	100000two
rd	$t0 = 8 = 01000two
rs	$t0 = 8 = 01000two
rt	$zero = 0 = 00000two

opcode(6)	rs(5)	rt(5)	rd(5)	sa(5)	function(6)
000000	01000	00000	01000	00000	100000

0000 0001 0000 0000 0100 0000 0010 0000 แปลงเป็นฐาน 16 ได้   01004020

b.

lw  $t1,  4($s3)	lw  rt, immediate(rs) (I-type)
Opcode	100011two
rt	$t1 = 9 = 01001two
Immediate	4 = 0000000000000100two
rs	$s3 = 19 = 10011two

opcode(6)	rs(5)	rt(5)	immediate(16)
100011	10011	01001	0000000000000100

1000 1110 0110 1001 0000 0000 0000 0100 เป็นฐาน 16 ได้   8E690004

2.10.5  What type (I-type, R-type) instruction do the instructions above represent?

a.  R-type

b. I-type

2.10.6  What is the hexadecimal representation of the opcode, rs, and rt fields in this instruction? For R-type instructions, what is the hexadecimal representation of the rd and funct fields? For I-type instructions, what is the hexadecimal representation of the immediate field?

a.      

Opcode	000000two	0hex
Function	100000two	20hex
rs	01000two	8hex
rt	00000two	0hex
rd	01000two	8hex

b.      

Opcode	100011two	23hex
rs	10011two	13hex
rt	01001two	9hex
Immediate	0000000000000100	4hex

2.11 In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to translate the entries into assembly code and determine what format of MIPS instruction the bits represent.

a. 0xAE0BFFFC

b. 0xBD08FFC0

2.11.1 What binary number does the above hexadecimal number represent?

a.       0xAE0BFFFC แปลงเป็นฐาน 2 ได้                         1010 1110 0000 1011 1111 1111 1111 1100          

b.       0xBD08FFC0 แปลงเป็นฐาน 2 ได้                        1000 1101 0000 1000 1111 1111 1100 0000          

2.11.2 What decimal number does the above hexadecimal number represent?

a.       0xAE0BFFFC แปลงเป็นฐาน 2 ได้                      1010 1110 0000 1011 1111 1111 1111 1100

แปลงเป็นฐาน 10                                                  -1374945284

b.       0xBD08FFC0 แปลงเป็นฐาน 2 ได้                     1000 1101 0000 1000 1111 1111 1100 0000

แปลงเป็นฐาน 10                                                  -1928790080

2.11.3 What instruction does the above hexadecimal number represent?

a.       0xAE0BFFFC แปลงเป็นฐาน 2 ได้                         1010 1110 0000 1011 1111 1111 1111 1100

opcode(6)	rs(5)	rt(5)	immediate(16)
101011	10000	01011	1111111111111100
sw	16	11	-4

sw  rt, immediate(rs)

sw  $11,-4($16)  หรือ  sw $t3, -4($s0)

b.       0xBD08FFC0 แปลงเป็นฐาน 2 ได้                        1000 1101 0000 1000 1111 1111 1100 0000

opcode(6)	rs(5)	rt(5)	immediate(16)
100011	01000	01000	1111111111000000
lw	8	8	-64

lw  rt, immediate(rs)

sw  $8,4($8)  หรือ  sw $t0, -64($t0)

In the following problems, the data table contains the values of various fields of MIPS instructions. You will be asked to determine what the instruction is, and find the MIPS format for the instruction

a. op=0, rs=1, rt=2, rd=3, shamt=0, funct=32

b. op=0x2B, rs=0x10, rt=0x5, const=0x4

2.11.4 What type (I-type, R-type) instruction do the instructions above represent?

a. R-type

b. I-type

2.11.5 What is the MIPS assembly instruction described above?

a.      

opcode(6)	rs(5)	rt(5)	rd(5)	sa(5)	function(6)
000000	00001	00010	00011	00000	100000
0	1	2	3	0	32

add  rd, rs, rt

add $3, $1, $2  หรือ  add $v1, $at, $v0

b.      

opcode(6)	rs(5)	rt(5)	immediate(16)
101011	10000	00101	0000000000000100
lw	16	5	4

sw  rt, immediate(rs)

sw  $5,4($16)  หรือ  sw $a1, 4($s0)

2.11.6 What is the binary representation of the instructions above?

a.       เป็นเลขฐาน 2 คือ 0000 0000 0010 0010 0001 1000 0010 0000

b.       เป็นเลขฐาน 2 คือ                 1010 1110 0000 0101 0000 0000 0000 0100

2.25

In this exercise, you will explore 32-bit constants in MIPS. For the following problems, you will be using the binary data in the table below.

a.       1010  1101  0001  0000  0000  0000  0000  0010two

b.       1111  1111  1111  1111  1111  1111  1111  1111two

2.25.1 Write the MIPS code that creates the 32-bit constants listed above and stores that value to register $t1

a. 1010  1101  0001  0000  0000  0000  0000  0010two  =  0xAD100002

Ans   add  $t1,$0,0xAD10002

b. 1111  1111  1111  1111  1111  1111  1111  1111two  =  0xFFFFFFFF

Ans   add  $t1,$0,0xFFFFFFFF

2.25.2 If the current value of the PC is 0x00000000, can you use a single jump instruction to get to the PC address as shown in the table above?

a. 1010  1101  0001  0000  0000  0000  0000  0010two  =  0xAD100002

     add  $t1,$0,0xAD10002

Ans   jr  $t1

b. 1111  1111  1111  1111  1111  1111  1111  1111two  =  0xFFFFFFFF

     add  $t1,$0,0xFFFFFFFF

Ans   jr  $t1

2.25.3 If the current value of the PC is 0x00000600, can you use a single branch instruction to get to the PC address as shown in the table above?

a. 1010  1101  0001  0000  0000  0000  0000  0010two  =  0xAD100002

     add  $t1,$0,0xAD10002

Ans   beq  $0,$0,$t1

b. 1111  1111  1111  1111  1111  1111  1111  1111two  =  0xFFFFFFFF

     add  $t1,$0,0xFFFFFFFF

Ans   beq  $0,$0,$t1

2.25.4 If the current value of the PC is 0x00400600, can you use a single branch instruction to get to the PC address as shown in the table above?

a. 1010  1101  0001  0000  0000  0000  0000  0010two  =  0xAD100002

     add  $t1,$0,0xAD10002

Ans   beq  $0,$0,$t1

b. 1111  1111  1111  1111  1111  1111  1111  1111two  =  0xFFFFFFFF

     add  $t1,$0,0xFFFFFFFF

Ans   beq  $0,$0,$t1

2.25.5 If the immediate field of a MIPS instruction was only 8 bits wide, write the MIPS code that creates the 32-bit constants listed above and stores that value to register $t1. Do not use the lui instruction.

a. 1010  1101  0001  0000  0000  0000  0000  0010two  =  0xAD100002

Ans

     add   $t1,$0,0xAD

     sll       $t1,$t1,24

     add   $t2,$0,0x10

     sll       $t2,$t2,16

     or       $t1,$t1,$t2

     add   $t2,$0,0x00

     sll       $t2,$t2,8

     or       $t1,$t1,$t2

     add   $t2,$0,0x02

     or       $t1,$t1,$t2

b. 1111  1111  1111  1111  1111  1111  1111  1111two  =  0xFFFFFFFF

Ans

     add   $t1,$0,0xFF

     sll       $t1,$t1,28

     add   $t2,$0,0xFF

     sll       $t2,$t2,16

     or       $t1,$t1,$t2

     add   $t2,$0,0xFF

     sll       $t2,$t2,8

     or       $t1,$t1,$t2

     add   $t2,$0,0xFF

     or       $t1,$t1,$t2

For the following problems, you will be using the MIPS assembly code as listed in the table

a.       lui  $t0,  0x1234

ori  $t0,  $t0,  0x5678

b.       ori  $t0,  $t0,  0x5678

lui  $t0,  0x1234

2.25.6       What is the value of register $t0 after the sequence of code in the table above?

a. lui  $t0,  0x1234

    ori  $t0,  $t0,  0x5678

Ans  $to  เก็บค่า   0x12345678

b. ori  $t0,  $t0,  0x5678

    lui  $t0,  0x1234

Ans  $t0  เก็บค่า  0x567c 

2.25.7 Write C code that is equivalent to the assembly code in the table. Assume that the largest constant that you can load into a 32-bit integer is 16 bits

a. lui  $t0,  0x1234

    ori  $t0,  $t0,  0x5678

Ans

    Int  V1,V2;

    V1 = 0x1234;

    V1 = V1 << 16;

    V2 = 0x5678;

    V1 = V1 | V2;

b. ori  $t0,  $t0,  0x5678

    lui  $t0,  0x1234

Ans

    Int  V1,V2;

    V1 = 0x1234;

    V2 = 0x5678;

    V1 = V1 | V2;

3.10

In a Von Neumann architecture, groups of bits have no intrinsic meanings by themselves. What a bit pattern represents depends entirely on how it is used. The following table shows bit patterns expressed in hexadecimal notation

a.       0x24A60004

b.       0xAFBF0000

3.10.1 What decimal number does the bit pattern represent if it is a two’s-complement integer? An unsigned integer?

a. 0x24A60004

Ans   two’s-complement และ unsigned integer = 614,858,756

b. 0xAFBF0000

Ans  unsigned integer = 2,949,578,752

         two’s-complement = -1,345,388,544

3.10.2 If this bit pattern is placed into the Instruction Register, what MIPS instruction will be executed?

a. 0x24A60004

Ans   add  $t1,$t1,0x24A60004

b.  0xAFBF0000

Ans   add  $t1,$t1,0xAFBF000

3.10.3  What decimal number does the bit pattern represent if it is a floating-point number? Use the IEEE754standard.

a.       0x24A60004  แปลงเป็นฐาน 2 ได้                      0010 0100 1010 0110 0000 0000 0000 0100

Sign(1)	Exponent(8)	Fraction(23)
0	01001001 = 73	01001100000000000000100 = 0.296875477

    (-2^sign) * (1+Fraction) * 2^eponent-127

    (-1^sign) ⁰ * (1+0.296875477) * 2(1^sign 73 -127) = 7.19910507 × 10^-17

b.       0xAFBF0000 แปลงเป็นฐาน 2 ได้                      1010 1111 1011 1111 0000 0000 0000 0000

Sign(1)	Exponent(8)	Fraction(23)
1	01011111 = 95	01111110000000000000000 = 0.4921875

   (-1^sign) * (1+Fraction) * 1 ^{Exponential-127}

    (-1¹) * (1+0.4921875) * 1^95-127 = -3.47426976 × 10^-10

The following table shows decimal numbers.

a.       -1609.5

b.       -938.8125

3.10.4 Write down the binary representation of the decimal number, assuming the IEEE 754 single precision format.

a.       -1609.5  แปลงเป็นฐาน 2 ได้               - 0110 0100 1001.1

                                                - 110 0100 1001.1 * 2⁰

                                                - 1.10 0100 10011 * 2¹⁰

                                                (-1^sign) * (1+Fraction) * 2^eponent-127

                                                -1¹* (1+0.10 0100 10011) * 2^137-127

Sign(1)	Exponent(8)	Fraction(23)
1	137 = 1000 1001	1001 0010 0110 0000 0000 000

Ans.        1100 0100 1100 1001 0011 0000 0000 0000

3.10.5 Write down the binary representation of the decimal number, assuming the IEEE 754 double precision format.

a.       -1609.5  แปลงเป็นฐาน 2 ได้               - 0110 0100 1001.1

                                                - 110 0100 1001.1 * 2^eponent-127

                                                - 1.10 0100 10011 * 2¹⁰

                                                -1^sign * (1+Fraction) * 2^eponent-127

                                                (-1¹)* (1+0.10 0100 10011) * 2^137-127

Sign(1)	Exponent(11)	Fraction(20)
1	137 = 0001000 1001	1001 0010 0110 0000 0000

Ans.        1000 1000 1001 1001 0010 0110 0000 0000

b.       -938.8125 แปลงเป็นฐาน 2 ได้           - 0011 1010 1010.1101

                                                - 0011 1010 1010.1101 * 1^sign                                                           -

                                                - 1.1101010101101 * 2⁹

                                                -1^sign * (1+Fraction) * 2^137-126

                                                (-1¹) * (1+0.1101010101101) * 2^136-127

Sign(1)	Exponent(11)	Fraction(20)
1	136 = 0001000 1000	1101 0101 0110 1000 0000

Ans         1000 1000 1000 1101 0101 0110 1000 0000

3.10.6 Write down the binary representation of the decimal number assuming it was stored using the single precision IBM format (base 16, instead of base 2, with 7 bits of exponent).

a.       -1609.5  แปลงเป็นฐาน 2 ได้               - 0110 0100 1001.1

                                                - 110 0100 1001.1 * 2^sign

                                                - 1.10 0100 10011 * 2¹⁰

                                                -1^sign * (1+Fraction) * 2^eponent-127

                                                -1¹ * (1+0.10 0100 10011) * 2^136-127

Sign(1)	Exponent(7)	Fraction(24)
1	1000011	1001 0010 0110 0000 0000 0000

Ans         1100 0100 1100 1001 0011 0000 0000 0000

b.       -938.8125 แปลงเป็นฐาน 2 ได้           - 0011 1010 1010.1101

                                                - 0011 1010 1010.1101 * 2⁰

                                                - 1.1101010101101 * 2⁹

                                                -1^sign * (1+Fraction) * 2^136-127

                                                -1¹ * (1+0.1101010101101) * 2^136-127

Sign(1)	Exponent(7)	Fraction(24)
1	1000011	1101 0101 0110 1000 0000 0000

Ans         1100 0100 0110 1010 1011 0100 0000 0000