Exercise 7
From text book chapter 4
Exercise 4.1
Different instructions utilize different hardware blocks in the basic single-cycle implementation The next three problems in this exercise refer to the following instruction
Instruction | Interpretation | |
a. | Add Rd, Rs, Rt | Reg[Rd]=Reg[Rs]+Reg[Rt] |
b. | Lw Rt, Offs(Rs) | Reg[Rt]=Mem[Reg[Rs]+Offs] |
4.1.1 What are the values of control signals generated by the control in Figure 4.2 for this instruction?
Ans
RegWrite | MemRead | ALUMux | MemWrite | ALUOp | RegMux | Branch | |
a. | 1 | 0 | 0(Reg) | 0 | Add | 1(ALU) | 0 |
b. | 1 | 1 | 1(Imm) | 0 | Add | 1(Mem) | 0 |
4.1.2 Which resources (blocks) perform a useful function for this instruction?
Ans
a.
ทุกอย่าง ยกเว้น Data Memory และ branch Add unit b.
ทุกอย่าง ยกเว้น branch Add unit และ second read port of the Register 4.1.3 Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?
Ans
Output ที่ไม่ได้ใช้งาน | ไม่มี Output | |
a. | Branch Add | Data Memory |
b. | Branch Add,second read port of the Register | None |
Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Latencies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. For the remaining three problems in this exercise, assume the following resource latencies:
I-Mem | Add | Mux | ALU | Regs | D-Mem | Control | |
a. | 400ps | 100ps | 30ps | 120ps | 200ps | 350ps | 100ps |
b. | 500ps | 150ps | 100ps | 180ps | 220ps | 1000ps | 65ps |
4.1.4 What is the critical path for a MIPS AND instruction?
Ans
a. Control
เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux b. Control
เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux 4.1.5 What is the critical path for a MIPS load (LD) instruction?
Ans
a. Control
เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, D-Mem, Mux b. Control
เร็วกว่า register ดังนั้น critical path คือ I-Mem, Regs, Mux, ALU, Mux 4.1.6 What is the critical path for a MIPS BEQ instruction?
Ans
a. path
แรก ยาวที่สุด(through Regs) b. path
แรก ยาวที่สุด(through Regs) Exercise 4.4
When implementing a logic expression in digital logic, one must use the available logic gates to implement an operator for which a gate is not available. Problems in this exercise refer to the following logic expressions:
Control signal 1 | Control signal 2 | |
a. | (((A OR B) OR C) OR (A AND C)) OR (A AND B) | (A OR B) OR C |
b. | (((A OR B) XOR B) OR (A OR C)) OR (A AND B) | A AND B |
4.4.1 Implement the logic for the Control signal 1. Your circuit should directly implement the given expression (do not reorganize the expression to “optimize” it), using NOT gates and 2-input AND, OR, and XOR gates.
Ans
a.
b.
4.4.2 Assuming that all gates have equal latencies, what is the length (in gates) of the critical path in your circuit from Exercise 4.4.1 ?
Ans
a. Latency in gates = 4
b. Latency in gates = 4
Exercise 4.9
In this exercise we examine the operation of the single-cycle datapath for a particular instruction. Problems in this exercise refer to the following MIPS instruction:
Instruction | |
a. | lw $1,40($6) |
b. | Label: bne $1,$2,Label |
4.9.1 What is the value of the instruction word?
Ans
Binary | Hexadecimal | |
a. | 100011 00110 00001 0000000000101000 | 8CC10028 |
b. | 000101 00001 00010 1111111111111111 | 1422FFFF |
a. 100011 00110 00001 0000000000101000 8CC10028
b. 000101 00001 00010 1111111111111111 1422FFFF
4.9.2 What is the register number supplied to the register file’s “Read register 1” input? Is this register actually read? How about “Read register 2”?
Ans
Read register 1 | Actually read? | Read register 2 | Actually read? | |
a. | 6 (00110 b) | Yes | 1 (00001 b) | Yes แต่ไม่ใช่ |
b. | 1 (00001 b) | Yes | 2 (00010 b) | Yes |
4.9.3 What is the register number supplied to the register file’s “Write register” input? Is this register actually written?
Ans
Read register 1 | Register actually written | |
a. | 1 (00001 b) | Yes |
b. | ไม่ทราบ เนื่องจาก ไม่ทราบ Register ปลายทาง | No |
Exercise 4.11
In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:
Instruction word | |
a. | 10001100010000110000000000010000 |
b. | 00010000001000110000000000001100 |
4.11.1 What are the outputs of the sign-extend and the jump “Shiftleft2” unit (in the upper left of Figure 4.24) for this instruction word?
Ans
sign-extend | jump “Shiftleft2” | |
a. | 00000000000000000000000000010000 | 0001000011000000000001000000 |
b. | 00000000000000000000000000001100 | 0000100011000000000000110000 |
4.11.2 What are the values of ALU control unit’s inputs for this instruction?
Ans
ALU control unit | instruction | |
a. | 00 | 010000 |
b. | 01 | 001100 |
4.11.3 What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.
Ans
new PC address | path through | |
a. | PC + 4 | PC > Add (PC+4) > branch Mux > jump Mux > PC |
b. | ถ้า $1 และ $3 ไม่เท่ากัน ให้ PC+4 | PC > Add (PC+4) > branch Mux หรือ PC > Add (PC+4) > Add (adds offset) > branch Mux |
The remaining problems in this exercise assume that data memory is all-zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched:
$0 | $1 | $2 | $3 | $4 | $5 | $6 | $8 | $12 | $31 | |
a. | 0 | 1 | 2 | 3 | -4 | 5 | 6 | 8 | 1 | -32 |
b. | 0 | -16 | -2 | -3 | 4 | -10 | -6 | -1 | 8 | -4 |
4.11.4 For each Mux, show the values of its data output during the execution of this instruction and these register values.
Ans
WrReg Mux | ALU Mux | Mem/ALU Mux | Branch Mux | Jump Mux | |
a. | 3 | 16 | 0 | PC+4 | PC+4 |
b. | 3 หรือ 0 | -3 | x | PC+4 | PC+4 |
4.11.5 For the ALU and the two add units, what are their data input values?
Ans
ALU | Add(PC+4) | Add(Branch) | |
a. | 2 และ 16 | PC และ 4 | PC+4 และ 16*4 |
b. | -16 และ -3 | PC และ 4 | PC+4 และ 12*4 |
4.11.6 What are the values of all inputs for the “Registers” unit?
Ans
Read Register1 | Read Register2 | Write Register | Write Data | RegWrite | |
a. | 2 | 3 | 3 | 0 | 1 |
b. | 1 | 3 | 3 หรือ 0 | X | 0 |
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